论文标题
不同长度的SEC-DED和SEC-DAEC代码的设计
Design of SEC-DED and SEC-DED-DAEC Codes of different lengths
论文作者
论文摘要
可靠性是通信和存储系统的重要要求。由于技术的连续规模，多个相邻位误差概率增加。由于软误差，数据可能会损坏。误差校正代码用于检测和纠正错误。在本文中，已经提出了不同数据长度的单个误差校正双误差检测（SEC-DED）和单个误差校正双误差检测双相邻误差校正（SEC-DED-DAEC）代码。与现有的编码方案相比，拟议的SEC-DED和SEC-DAEC代码需要较低的延迟和功率。已经提出了有关建议和现有代码的逻辑门的区域复杂性。与现有的SEC-DED代码相比，基于ASIC的合成结果显示出显着降低。所有编解码器架构均在ASIC平台上合成。不同的SEC-DAEC代码的性能是根据面积，功率和延迟来表达的。
Reliability is an important requirement for both communication and storage systems. Due to continuous scale down of technology multiple adjacent bits error probability increases. The data may be corrupted due soft errors. Error correction codes are used to detect and correct the errors. In this paper, design of single error correction-double error detection (SEC-DED) and single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes of different data lengths have been proposed. Proposed SEC-DED and SEC-DED-DAEC codes require lower delay and power compared to existing coding schemes. Area complexity in terms of logic gates of proposed and existing codes have been presented. ASIC-based synthesis results show a notable reduction compared to existing SEC-DED codes. All the codec architectures are synthesized on ASIC platform. Performances of different SEC-DED-DAEC codes are tabulated in terms of area, power and delay.
