论文标题
使用可配置的TLB层次结构启用RISC-V的虚拟内存研究
Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator
论文作者
论文摘要
火箭芯片生成器使用参数化处理器组件的集合来生产基于RISC-V的SOC。它是一种强大的工具，可以生产从微小嵌入式处理器到复杂的多核系统的各种处理器设计。在本文中，我们扩展了火箭芯片发生器的内存管理单元的功能，尤其是TLB层次结构。 TLB在性能方面至关重要，因为它们可以减轻频繁的页面桌面步行的开销，但由于其大小和/或关联性，可能会损害处理器的关键路径。在原始的火箭芯片实现中，L1指令/数据TLB具有完全缔合性，共享L2 TLB是直接映射的。我们提高这些限制并设计并实施可配置的，设置缔合的L1和L2 TLB模板，这些模板可以创建任何组织，从直接映射到完全缔合性，以实现所需的性能和资源利用率，尤其是对于较大的TLB。我们使用Xilinx ZCU102 FPGA上的Spec2006 Suite的基准评估了设计的不同TLB配置以及设计的当前性能，区域和频率结果。
The Rocket Chip Generator uses a collection of parameterized processor components to produce RISC-V-based SoCs. It is a powerful tool that can produce a wide variety of processor designs ranging from tiny embedded processors to complex multi-core systems. In this paper we extend the features of the Memory Management Unit of the Rocket Chip Generator and specifically the TLB hierarchy. TLBs are essential in terms of performance because they mitigate the overhead of frequent Page Table Walks, but may harm the critical path of the processor due to their size and/or associativity. In the original Rocket Chip implementation the L1 Instruction/Data TLB is fully-associative and the shared L2 TLB is direct-mapped. We lift these restrictions and design and implement configurable, set-associative L1 and L2 TLB templates that can create any organization from direct-mapped to fully-associative to achieve the desired ratio of performance and resource utilization, especially for larger TLBs. We evaluate different TLB configurations and present performance, area, and frequency results of our design using benchmarks from the SPEC2006 suite on the Xilinx ZCU102 FPGA.
