论文标题

用于高速链接设计的开源合成模拟块:20-gs/s 5b应附类似物对数字转换器和5-GHz相位插值器

Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator

论文作者

Kim, Sung-Jin, Myers, Zachary, Herbst, Steven, Lim, ByongChan, Horowitz, Mark

论文摘要

Using digital standard cells and digital place-and-route (PnR) tools, we created a 20 GS/s, 8-bit analog-to-digital converter (ADC) for use in high-speed serial link applications with an ENOB of 5.6, a DNL of 0.96 LSB, and an INL of 2.39 LSB, which dissipated 175 mW in 0.102 mm2 in a 16nm technology.该设计完全由HDL描述,因此可以以最少的精力将其移植到其他过程中,并作为开源。

Using digital standard cells and digital place-and-route (PnR) tools, we created a 20 GS/s, 8-bit analog-to-digital converter (ADC) for use in high-speed serial link applications with an ENOB of 5.6, a DNL of 0.96 LSB, and an INL of 2.39 LSB, which dissipated 175 mW in 0.102 mm2 in a 16nm technology. The design is entirely described by HDL so that it can be ported to other processes with minimal effort and shared as open source.

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