论文标题

2输入4输出可编程自旋波逻辑门

2-input 4-output Programmable Spin Wave Logic Gate

论文作者

Mahmoud, Abdulqader, Vanderveken, Frederic, Adelmann, Christoph, Ciubotaru, Florin, Hamdioui, Said, Cotofana, Sorin

论文摘要

为了将基于自旋波(SW)的计算范式带入实践,并开发超低功率横尼克电路和计算平台,人们需要在SW域内运行并可以级联的基本逻辑门,而无需在SW和电压域之间来回转换。为了实现这一目标,SW门必须具有固有的粉丝功能,是输入输出数据表示相干,并且可以重新配置。在本文中,我们解决了第一个和最后的要求,并提出了一种新颖的4输出可编程SW逻辑。首先,我们介绍了栅极结构并证明,通过调整门输出检测方法,它可以与2输入布尔函数集的任何4个元素子集以及NAND或NAND或NOR,NOR,NOR,NOR,XOR和XNOR相称。此外,我们调整了结构,以使其所有4个输出产生具有相同能量的SWS,并证明它可以评估布尔功能集,同时提供粉丝功能在1到4之间。我们通过实例化和模拟不同的门配置来验证我们的方法。面向对象的微型框架(OOMMF)模拟的模拟。最后,我们在延迟和能耗方面评估了提案的绩效,并将其与现有的最新SW和16NM CMOS对应物进行了比较。结果表明,与常规的SW和16NM CMOS实施相比,我们的方法可提供3倍和16X的能量降低。

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

扫码加入交流群

加入微信交流群

微信交流群二维码

扫码加入学术交流群,获取更多资源