论文标题
研究Intel FPGA SDK中自动优化的潜力
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL
论文作者
论文摘要
高级合成（HLS）工具，例如用于OPENCL的Intel FPGA SDK，提高设计生产力并启用受简单程序指令（Pragmas）指导的有效设计空间探索，但有时可能会错过高性能所需的重要优化。在本文中，我们介绍了HLS优化中的权衡方面的研究，以及现代HLS工具在自动优化应用程序中的潜力。我们使用Intel FPGA SDK和Arria 10 FPGA开发套件在5阶段的ISP管道上进行研究。我们表明，HLS工具中的自动优化是有价值的，在同等的CPU执行中实现了高达2.7倍的速度。但是，通过进一步的手动调整，我们可以在CPU上实现高达36.5倍的速度。我们绘制了几个有关自动优化的有效性的特定课程，并以简单指令指导的性质以及高性能所需的手动重写的性质。
High Level Synthesis (HLS) tools, like the Intel FPGA SDK for OpenCL, improve design productivity and enable efficient design space exploration guided by simple program directives (pragmas), but may sometimes miss important optimizations necessary for high performance. In this paper, we present a study of the tradeoffs in HLS optimizations, and the potential of a modern HLS tool in automatically optimizing an application. We perform the study on a 5-stage camera ISP pipeline using the Intel FPGA SDK for OpenCL and an Arria 10 FPGA Dev Kit. We show that automatic optimizations in the HLS tool are valuable, achieving a up to 2.7X speedup over equivalent CPU execution. With further hand tuning, however, we can achieve up to 36.5X speedup over CPU. We draw several specific lessons about the effectiveness of automatic optimizations guided by simple directives, and the nature of manual rewriting required for high performance.
