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Many fabless semiconductor companies outsource their designs to third-party fabrication houses. As trustworthiness of chain after outsourcing including fabrication houses is not established, any adversary in between, with malicious intent may tamper the design by inserting Hardware Trojans (HTs). Detection of such HTs is of utmost importance to assure the trust and integrity of the chips. However, the efficiency of detection techniques based on side-channel analysis is largely affected by process variations. In this paper, a methodology for detecting HTs by analyzing the delays of topologically symmetric paths is proposed. The proposed technique, rather than depending on golden ICs as a reference for HT detection, employs the concept of self-referencing. In this work, the fact that delays of topologically symmetric paths in an IC will be affected similarly by process variations is exploited. A procedure to chose topologically symmetric paths that are minimally affected by process variations is presented. Further, a technique is proposed to create topologically symmetric paths by inserting extra logic gates if such paths do not exist in the design intrinsically. Simulations performed on ISCAS-85 benchmarks establish that the proposed method is able to achieve a true positive rate of 100% with a false positive rate less than 3%. In our experimentation, We have considered the maximum of 15% intra-die and 20% inter-die variations in threshold voltage (Vth).