论文标题
互连的寄生虫和在全部记忆中计算体系结构中的分区
Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures
论文作者
论文摘要
由于耗尽能源的信号转换单元，在同一内存阵列内实现矩阵向量乘法和非线性矢量操作的全部内存计算（IMC）体系结构在同一内存阵列中同时实现了矩阵 - 矢量乘法和非线性矢量操作。但是，在整个深神经网络（DNN）中维持模拟域中的计算具有对互连寄生虫的潜在敏感性。因此，在本文中，我们研究了电线寄生抗性和电容对部署在全轴IMC体系结构上的DNN模型准确性的影响。此外，我们提出了一种分区机制，以减轻寄生虫的影响，同时通过将大型阵列分为多个分区来保留模拟域中的计算。在完全纳入IMC电路上部署的400 x 120 x 84 x 10 DNN模型的Spice电路模拟结果表明，对于16、8和8的水平分区，可以实现94.84％的准确性，并在16、8和8的水平分区中获得8、8、8和1垂直分区，并分为9 nnn的第三级别的dnn，〜9是〜9的dnn，〜9 CPU上的数字实施。结果表明，由于处理分区所需的额外电路，以更高的功耗为代价实现了准确的好处。
Fully-analog in-memory computing (IMC) architectures that implement both matrix-vector multiplication and non-linear vector operations within the same memory array have shown promising performance benefits over conventional IMC systems due to the removal of energy-hungry signal conversion units. However, maintaining the computation in the analog domain for the entire deep neural network (DNN) comes with potential sensitivity to interconnect parasitics. Thus, in this paper, we investigate the effect of wire parasitic resistance and capacitance on the accuracy of DNN models deployed on fully-analog IMC architectures. Moreover, we propose a partitioning mechanism to alleviate the impact of the parasitic while keeping the computation in the analog domain through dividing large arrays into multiple partitions. The SPICE circuit simulation results for a 400 X 120 X 84 X 10 DNN model deployed on a fully-analog IMC circuit show that a 94.84% accuracy could be achieved for MNIST classification application with 16, 8, and 8 horizontal partitions, as well as 8, 8, and 1 vertical partitions for first, second, and third layers of the DNN, respectively, which is comparable to the ~97% accuracy realized by digital implementation on CPU. It is shown that accuracy benefits are achieved at the cost of higher power consumption due to the extra circuitry required for handling partitioning.
