论文标题
通过门合并和框架优化估算更快的诞生概率估算
Faster Born probability estimation via gate merging and frame optimisation
论文作者
论文摘要
通过经典方法估计结果概率估算是验证量子计算设备的重要任务。任何量子电路的结果概率可以使用蒙特卡洛采样估算，其中电路框架表示中存在的负性量量化了达到一定精度所需的样品数量的开销。在本文中，我们提出了两个经典的子列表：电路门合并和框架优化，它们优化了电路表示以减少抽样开销。我们表明，两个子路线的运行时间在电路尺寸和门深度上是多项式尺度的。我们的方法适用于通用电路，而不论生成门集，Qudit尺寸和电路组件的选定框架表示。我们从数值上证明，对于所有带有Clifford+$ t $和Haar随机门的随机电路案例，我们的方法在负面的开销中提供了改进的缩放，并且我们方法的性能与先前的Quasi-Probability Simulators相比，作为非clifford gates的数量增加。
Outcome probability estimation via classical methods is an important task for validating quantum computing devices. Outcome probabilities of any quantum circuit can be estimated using Monte Carlo sampling, where the amount of negativity present in the circuit frame representation quantifies the overhead on the number of samples required to achieve a certain precision. In this paper, we propose two classical sub-routines: circuit gate merging and frame optimisation, which optimise the circuit representation to reduce the sampling overhead. We show that the runtimes of both sub-routines scale polynomially in circuit size and gate depth. Our methods are applicable to general circuits, regardless of generating gate sets, qudit dimensions and the chosen frame representations for the circuit components. We numerically demonstrate that our methods provide improved scaling in the negativity overhead for all tested cases of random circuits with Clifford+$T$ and Haar-random gates, and that the performance of our methods compares favourably with prior quasi-probability simulators as the number of non-Clifford gates increases.
