论文标题
VWR2A：低功率嵌入式设备的非常宽的可重构阵列架构
VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices
论文作者
论文摘要
边缘计算需要高性能的嵌入式系统。固定功能或自定义加速器（例如FFT或FIR滤波器发动机）非常有效地为给定的一组约束实施特定功能。但是，在面对整个应用的优化或功能升级时，它们是不灵活的。相反，可编程核心具有更高的灵活性，但通常会受到区域，性能和尤其是能源消耗的惩罚。在本文中，我们提出了VWR2A，该体系结构集成了较高的计算密度和低功率存储器结构（即非常宽的寄存器和ScratchPad记忆）。 VWR2A在FFT内核上相对于FFT加速器，在FFT内核上以相似或更好的性能缩小了能量差距。此外，VWR2A灵活性允许加速多个内核，从而在应用级别节省大量能源。
Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, they are inflexible when facing application-wide optimizations or functionality upgrades. Conversely, programmable cores offer higher flexibility, but often with a penalty in area, performance, and, above all, energy consumption. In this paper, we propose VWR2A, an architecture that integrates high computational density and low power memory structures (i.e., very-wide registers and scratchpad memories). VWR2A narrows the energy gap with similar or better performance on FFT kernels with respect to an FFT accelerator. Moreover, VWR2A flexibility allows to accelerate multiple kernels, resulting in significant energy savings at the application level.
