论文标题
乘数减少了活动，并最小化内部产品阵列的互连
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays
论文作者
论文摘要
我们提出了一个管道的乘数，具有减少的活动，并基于在线数字式算术算术最小化互连。工作精度已被截断，以便使用$ p <n $位用于计算$ n $ bits产品，从而节省了大量的面积和电源。数字切片根据输入遵循可变精度，增加了$ p $，然后根据错误配置文件减小。已完成管道来实现高吞吐量和低潜伏期，这对于计算密集的内部产品是理想的选择。提出的设计的综合结果已被介绍，并将其与非涉及的在线乘法器，管道上的在线乘法器进行了比较，并具有完整的工作精度和常规的序列 - 并行和阵列乘数。与管道插入的在线乘数相比，以8、16、24 $和32美元的位精度，分别为$ 38 \％$和$ 44 \％$减少的功率和面积的$ 38 \％\％$ $降低，而没有工作精确截断。
We present a pipelined multiplier with reduced activities and minimized interconnect based on online digit-serial arithmetic. The working precision has been truncated such that $p<n$ bits are used to compute $n$ bits product, resulting in significant savings in area and power. The digit slices follow variable precision according to input, increasing upto $p$ and then decreases according to the error profile. Pipelining has been done to achieve high throughput and low latency which is desirable for compute intensive inner products. Synthesis results of the proposed designs have been presented and compared with the non-pipelined online multiplier, pipelined online multiplier with full working precision and conventional serial-parallel and array multipliers. For $8, 16, 24$ and $32$ bit precision, the proposed low power pipelined design show upto $38\%$ and $44\%$ reduction in power and area respectively compared to the pipelined online multiplier without working precision truncation.
