论文标题

基于二维NTT的块 - 平行收缩 - 阵列架构

Block-Parallel Systolic-Array Architecture for 2-D NTT-based Fragile Watermark Embedding

论文作者

Madanayake, H. P. L. Arjuna, Cintra, R. J., Dimitrov, V. S., Bruton, L.

论文摘要

数字理论变换(NTTS)已应用于数字图像的脆弱水印。提出了基于二维特殊Hartley NTT(HNTT)的块 - 平行收缩式阵列结构。拟议的核心使用两个2-D特殊HNTT硬件核,每种核心使用$ \ Mathrm {gf}(3)$使用数字算术,并处理$ 4 \ times4 $ block的像素块在每个时钟周期中并行。原型在Xilinx SX35-10FF668 FPGA设备上运行。 FPGA电路的最大估计吞吐量为1亿美元$ 4 \ times4 $ hntt脆弱的水印块,每秒以100 MHz为单位。潜在的应用程序存在于处理大量受保护的数字图像的高流量后端服务器中,需要身份验证,在高安全性监视应用中,在实时视频处理国家安全性质或事务的信息中,在企业客户的视频/摄影客户管理中,对娱乐性的娱乐行业和娱乐性竞争,在娱乐业和娱乐行业中进行了良好的材料,以及在娱乐行业中,在娱乐业中,在娱乐业中进行了良好的娱乐性,以及在电子企业方面进行了娱乐性,并在娱乐行业中进行了旨在的娱乐界,并将其用于电子娱乐行业。

Number-theoretic transforms (NTTs) have been applied in the fragile watermarking of digital images. A block-parallel systolic-array architecture is proposed for watermarking based on the 2-D special Hartley NTT (HNTT). The proposed core employs two 2-D special HNTT hardware cores, each using digital arithmetic over $\mathrm{GF}(3)$, and processes $4\times4$ blocks of pixels in parallel every clock cycle. Prototypes are operational on a Xilinx Sx35-10ff668 FPGA device. The maximum estimated throughput of the FPGA circuit is 100 million $4\times4$ HNTT fragile watermarked blocks per second, when clocked at 100 MHz. Potential applications exist in high-traffic back-end servers dealing with large amounts of protected digital images requiring authentication, in remote-sensing for high-security surveillance applications, in real-time video processing of information of a sensitive nature or matters of national security, in video/photographic content management of corporate clients, in authenticating multimedia for the entertainment industry, in the authentication of electronic evidence material, and in real-time news streaming.

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