论文标题
对$ HFO_2/si $接口的调查：材料科学挑战及其对MOSFET设备性能的影响
An Investigation into the $HfO_2/Si$ Interface: Materials Science Challenges and their Effects on MOSFET Device Performance
论文作者
论文摘要
自1960年代以来，戈登·摩尔（Gordon Moore）提出，我们的电子设备中的晶体管密度应每两年一倍，而成本减半，半导体行业将这一说法充满了心。在过去的几十年中，没有其他行业看到的增长甚至与半导体行业经历的增长相对接近。聪明的头脑不懈地努力缩小晶体管的聪明人，这一切都使这一切成为可能。其中最新的是使用高K介电和返回金属大门与3D横向器建筑结合在一起。这是从90 nm节点过渡到45 nm节点的过渡，使我们能够进一步缩小晶体管而不会失去其他门控制。与SIO2相比，使用高K门电介质的基本原因是进一步缩小我们的门氧化物已经在几个埃埃斯特罗姆斯上，不再是获得额外栅极控制的可行选择。 High-K介电通过利用电容器的基本物理和电介质科学来克服这一点，以提供可行的选择，以增加栅极控制，而无需连续较薄的门氧化物。氧化物是研究最多，受到此类材料的流行。其高介电常数〜16-25及其在工作温度下与硅的接口稳定性使其成为当前CMOS技术中使用的理想候选者。尽管外观很简单，但在制造此类高K HFO2/Si界面中涉及的过程充满了过程微妙和细微差别。在本术语中，我们希望探索这些高K HFO2/SI接口的物理和材料科学，讨论在实际制造实际制造时克服它们的挑战和方式，以及这如何最终影响我们的设备性能。
Since the 1960's when Gordon Moore proposed that the transistor density in our electronic devices should double every two years while the cost is halved, the semiconductor industry has taken this statement to heart. Over the last few decades, no other industry has seen growth even comparably close to that experienced by the semiconductors industry. This has all been made possible by the unbroken string of ingenious breakthroughs by brilliant minds that have been working tirelessly to shrink down transistors. The latest of which is the use of high-k dielectrics and a return to metal gates combined with 3D-transistor architectures. This has been the enabling technology for the transition from the 90 nm node to the 45 nm node, allowing us to shrink our transistors further without losing additional gate control. The fundamental reason for using a high-k gate dielectric compared to SiO2 is that shrinking our gate oxide further, which is already at a few angstroms, is no longer a feasible option to gain additional gate control. High-k dielectric overcome this by exploiting the fundamental physics of capacitors and the materials science of dielectrics to provide a viable option to increase gate control without the need for successively thinner gate oxides. Hafnium Oxide is the most studied and popular of such materials. Its high dielectric constant ~16-25 and interface stability with silicon at operating temperatures make it an ideal candidate for use in current CMOS technology. Despite its deceivingly simple appearance, the processes involved in the fabrication of such high-k HfO2/Si interfaces are full of process subtleties and nuances. In this term paper we hope to explore the physics and materials science of these high-k HfO2/Si interfaces, discussing the challenges and ways to overcome them when it comes to its actual fabrication, and how this ultimately affects our device performance.
