论文标题
ECI：用于混合FPGA-CPU架构的可自定义的缓存相干堆栈
ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures
论文作者
论文摘要
与其他加速器不同，FPGA能够支持高速缓存相干性，从而将它们变成更强大的建筑选择，而不仅仅是外围加速器。但是，大多数现有的FPGA部署是非缓存相干的，或仅支持从CPU控制缓存相干性的不对称设计。利用最近发布的两个插座CPU-FPGA体系结构，在本文中，我们描述了ECI，在FPGA上可以灵活地实现可支持对称和非对称协议的FPGA。 ECI是开放且可定制的，鉴于应用程序是与高速缓存相干协议完全互动的机会，从而为现有设计中没有可用的许多有趣的系统设计和研究机会开放。通过广泛的微型计算，我们表明ECI表现出竞争激烈的性能，并详细讨论一个用例，说明了在FPGA上拥有开放的高速缓存相干堆栈的好处。
Unlike other accelerators, FPGAs are capable of supporting cache coherency, thereby turning them into a more powerful architectural option than just a peripheral accelerator. However, most existing deployments of FPGAs are either non-cache coherent or support only an asymmetric design where cache coherency is controlled from the CPU. Taking advantage of a recently released two socket CPU-FPGA architecture, in this paper we describe ECI, a flexible implementation of cache coherency on the FPGA capable of supporting both symmetric and asymmetric protocols. ECI is open and customizable, given applications the opportunity to fully interact with the cache coherency protocol, thereby opening up many interesting system design and research opportunities not available in existing designs. Through extensive microbenchmarks we show that ECI exhibits highly competitive performance and discuss in detail one use-case illustrating the benefits of having an open cache coherency stack on the FPGA.
