论文标题

E-G2C:0.14至8.31 $μ$ j/temperion nn的处理器,具有连续的芯片适应以进行异常检测和EGM的ECG转换

e-G2C: A 0.14-to-8.31 $μ$J/Inference NN-based Processor with Continuous On-chip Adaptation for Anomaly Detection and ECG Conversion from EGM

论文作者

Zhao, Yang, Zhang, Yongan, Fu, Yonggan, Ouyang, Xu, Wan, Cheng, Wu, Shang, Banta, Anton, John, Mathews M., Post, Allison, Razavi, Mehdi, Cavallaro, Joseph, Aazhang, Behnaam, Lin, Yingyan

论文摘要

这项工作介绍了第一个硅验证的专用EGM至ECG(G2C)处理器,称为E-G2C,具有连续的轻质异常检测,事件驱动的粗/精确转换和芯片适应。 e-G2C utilizes neural network (NN) based G2C conversion and integrates 1) an architecture supporting anomaly detection and coarse/precise conversion via time multiplexing to balance the effectiveness and power, 2) an algorithm-hardware co-designed vector-wise sparsity resulting in a 1.6-1.7$\times$ speedup, 3) hybrid dataflows for enhancing near 100% utilization for正常/深度(DW)/点(PW)卷积(Convs)和4)片上检测阈值适应引擎,以实现连续有效性。实现的0.14-8.31 $μ$ J/推理能源效率在相似的复杂性下优于先前的艺术,有望实时检测/转换以及可能的关键生活干预措施

This work presents the first silicon-validated dedicated EGM-to-ECG (G2C) processor, dubbed e-G2C, featuring continuous lightweight anomaly detection, event-driven coarse/precise conversion, and on-chip adaptation. e-G2C utilizes neural network (NN) based G2C conversion and integrates 1) an architecture supporting anomaly detection and coarse/precise conversion via time multiplexing to balance the effectiveness and power, 2) an algorithm-hardware co-designed vector-wise sparsity resulting in a 1.6-1.7$\times$ speedup, 3) hybrid dataflows for enhancing near 100% utilization for normal/depth-wise(DW)/point-wise(PW) convolutions (Convs), and 4) an on-chip detection threshold adaptation engine for continuous effectiveness. The achieved 0.14-8.31 $μ$J/inference energy efficiency outperforms prior arts under similar complexity, promising real-time detection/conversion and possibly life-critical interventions

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