论文标题
类似CMOL的Memristor-CMOS神经形态芯片核心，证明了随机二进制STDP
A CMOL-Like Memristor-CMOS Neuromorphic Chip-Core Demonstrating Stochastic Binary STDP
论文作者
论文摘要
Nanoscale Memristors的出现引起了人们的希望，能够构建CMOL（CMOS/纳米线/分子）类型的超密集内存内计算电路体系结构。在CMOL，纳米级备忘录将在纳米线的交叉点进行制造。 CMOL概念可以通过在CMO上制造低密度神经元并在顶部进行了制造后使用纳米线和纳米级 - 磁性织物来利用CMOL概念在神经形态硬件中利用。但是，技术问题阻碍了此类发展，目前可靠的商业单片CMOS-MEMRISTOR技术。一方面，每个备忘录都需要串联的MOS选择器晶体管，以确保大型阵列形成和编程操作。这会导致复合Mos-Memristor突触（称为1T1R），这些突触不再是纳米线穿越时突触。另一方面，备忘录尚未构成高度可靠，稳定的模拟记忆，用于逐渐学习的大规模模拟重量突触。 Here we demonstrate a pseudo-CMOL monolithic chip core that circumvents the two technical problems mentioned above by (a) exploiting a CMOL-like geometrical chip layout technique to improve density despite the 1T1R limitation, and (b) exploiting a binary weight stochastic Spike-Timing-Dependent-Plasticity (STDP) learning rule that takes advantage of the more reliable binary memory capability of the memristors 用过的。为尖峰神经网络（SNN）CMOL核心提供了实验结果，该核心具有64个输入神经元，64个输出神经元和4096 1T1R突触，该突触在130nm CMOS中制造，顶部为200nm尺寸的Ti/HFox/Tin Memristors。 CMOL核使用查询驱动的事件读取，这允许Memristor变异性不敏感的计算。
The advent of nanoscale memristors raised hopes of being able to build CMOL (CMOS/nanowire/moLecular) type ultra-dense in-memory-computing circuit architectures. In CMOL, nanoscale memristors would be fabricated at the intersection of nanowires. The CMOL concept can be exploited in neuromorphic hardware by fabricating lower-density neurons on CMOS and placing massive analog synaptic connectivity with nanowire and nanoscale-memristor fabric post-fabricated on top. However, technical problems have hindered such developments for presently available reliable commercial monolithic CMOS-memristor technologies. On one hand, each memristor needs a MOS selector transistor in series to guarantee forming and programming operations in large arrays. This results in compound MOS-memristor synapses (called 1T1R) which are no longer synapses at the crossing of nanowires. On the other hand, memristors do not yet constitute highly reliable, stable analog memories for massive analog-weight synapses with gradual learning. Here we demonstrate a pseudo-CMOL monolithic chip core that circumvents the two technical problems mentioned above by (a) exploiting a CMOL-like geometrical chip layout technique to improve density despite the 1T1R limitation, and (b) exploiting a binary weight stochastic Spike-Timing-Dependent-Plasticity (STDP) learning rule that takes advantage of the more reliable binary memory capability of the memristors used. Experimental results are provided for a spiking neural network (SNN) CMOL-core with 64 input neurons, 64 output neurons, and 4096 1T1R synapses, fabricated in 130nm CMOS with 200nm-sized Ti/HfOx/TiN memristors on top. The CMOL-core uses query-driven event read-out, which allows for memristor variability insensitive computations.
