论文标题
低功率1 GB/S线驱动器，具有可配置的有损耗传输线的预先强调
A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines
论文作者
论文摘要
具有可配置前重点的线驱动程序是在65 nm CMOS过程中实现的。驱动程序使用三击进料式均衡（FFE）体系结构。 TAP之间的相对延迟可通过8阶段延迟锁定环（DLL）和数字插值器以单位间隔（UI）的1/16的增量选择。也可以通过八个端系（SST）驱动程序的可编程阵列来控制每个点击的输出振幅和源阻抗。整个设计以1 GB/s的1.2 V电源消耗9兆瓦。
A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.
