论文标题
六边形：用优化的chiplet排列到数百个chiplets
HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement
论文作者
论文摘要
2.5D集成是解决高级技术节点中制造芯片不断增长的成本的重要技术。这构成了提供高性能芯片间互连（ICIS）的挑战。随着芯片的数量成长为数十个或数百个，以最大化ICI性能的方式将其布置进行彻底优化。在本文中，我们提出了六角形，这是一种比理论上胜过网格布置的芯片的布置（网络直径降低了42％；一分为二的带宽提高了130％）和实际上（延迟降低了19％；吞吐量提高；吞吐量提高了34％）。 Mexamesh启用具有高性能ICIS的大规模chiplet设计。
2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects (ICIs). As the number of chiplets grows to tens or hundreds, it becomes infeasible to hand-optimize their arrangement in a way that maximizes the ICI performance. In this paper, we propose HexaMesh, an arrangement of chiplets that outperforms a grid arrangement both in theory (network diameter reduced by 42%; bisection bandwidth improved by 130%) and in practice (latency reduced by 19%; throughput improved by 34%). MexaMesh enables large-scale chiplet designs with high-performance ICIs.
