论文标题
使用硬件有效的机器学习体系结构缩放量子读数
Scaling Qubit Readout with Hardware Efficient Machine Learning Architectures
论文作者
论文摘要
读取量子是量子计算中的基本操作。它将量子信息转化为经典信息,使后续分类可以分配量子状态“ 0”或“ 1”。不幸的是,Qubit读数是超导量子处理器上最容易出错,最慢的操作之一。在最先进的超导量子处理器上,读数错误的范围为1-10%。高读数准确性对于实现近期嘈杂量子计算机和未来错误校正量子计算机的高保真度至关重要。 先前的工作使用了机器学习辅助的单杆Qubit-State分类,在该分类中,通过补偿串扰误差,将深层神经网络用于更强大的歧视。但是,神经网络大小可以限制系统的可扩展性,尤其是在需要快速硬件歧视的情况下。这种最先进的基线设计不能在用于控制和读数超导QUBITS的现成的FPGA上实现,这在大多数系统中会增加整体读数潜伏期,因为必须在软件中执行歧视。 在这项工作中,我们提出了Herqules,这是一种可扩展的方法,可以通过使用匹配的过滤器的层次结构以及明显较小且可扩展的神经网络来改善Qubit-State歧视,以进行Qubit-State Inclimination。我们的读数准确度(相对改进为16.4%)比基线具有可扩展设计,可以在现成的FPGA上很容易实现。我们还表明,与基线设计相比,HERQULES更具用途,并且可以支持较短的读数持续时间,而无需其他培训开销。
Reading a qubit is a fundamental operation in quantum computing. It translates quantum information into classical information enabling subsequent classification to assign the qubit states `0' or `1'. Unfortunately, qubit readout is one of the most error-prone and slowest operations on a superconducting quantum processor. On state-of-the-art superconducting quantum processors, readout errors can range from 1-10%. High readout accuracy is essential for enabling high fidelity for near-term noisy quantum computers and error-corrected quantum computers of the future. Prior works have used machine-learning-assisted single-shot qubit-state classification, where a deep neural network was used for more robust discrimination by compensating for crosstalk errors. However, the neural network size can limit the scalability of systems, especially if fast hardware discrimination is required. This state-of-the-art baseline design cannot be implemented on off-the-shelf FPGAs used for the control and readout of superconducting qubits in most systems, which increases the overall readout latency as discrimination has to be performed in software. In this work, we propose HERQULES, a scalable approach to improve qubit-state discrimination by using a hierarchy of matched filters in conjunction with a significantly smaller and scalable neural network for qubit-state discrimination. We achieve substantially higher readout accuracies (16.4% relative improvement) than the baseline with a scalable design that can be readily implemented on off-the-shelf FPGAs. We also show that HERQULES is more versatile and can support shorter readout durations than the baseline design without additional training overheads.