论文标题
用于微波动力学检测器的基于RF-SOC的读数系统的建模结果和基线设计
Modeling Results and Baseline Design for an RF-SoC-Based Readout System for Microwave Kinetic Inductance Detectors
论文作者
论文摘要
本文以现有的信号处理技术和开源软件为基础，为基于低温检测器的时空光谱焦平面仪器介绍了RF系统频率频率读数的基线设计。提出了对不同FPGA载体板的权衡分析，以寻找一种最佳的下一代解决方案，以读取更大的微波动力学电感探测器（MKIDS）。选择了Xilinx的ZCU111 RF SOC FPGA董事会，并显示了该集成系统如何有望增加可以读取的像素的数量（每板），从而可以降低每个像素，质量和量和功耗的读数成本，以及所有这些对于使Mkid Instruments对Mkid Instrument of Cloesseply andloplaise cloesseply andlopeplaine coase coase coase coase cloes coase coase coase coes coase coes coase coes coase coes coase coase coes coase coes coase corplay and coaste and coalte and corts又很重要。片上逻辑能力显示出对可以使用此新系统读取，引导和处理的MKID数量的主要约束。因此，分析了新颖的信号处理技术，包括数字降低转换（DDC）校正的下最大脱落的采样，以减少逻辑要求而不损害信号与噪声比率。还展示了将ZCU111板与次级FPGA板组合使用，将允许使用所有8个ADC和8个DAC，提供足够的带宽，以阅读每板设置多达8,000个MKID，比最先进的ART进行8倍改进，并且重要的是追求100,000 Pixel阵列。最后，研究了将MKID的操作频率范围扩展到5-10 GHz制度（或可能超出）的可行性，并提出了这样做的一些好处和后果。
Building upon existing signal processing techniques and open-source software, this paper presents a baseline design for an RF System-on-Chip Frequency Division Multiplexed readout for a spatio-spectral focal plane instrument based on low temperature detectors. A trade-off analysis of different FPGA carrier boards is presented in an attempt to find an optimum next-generation solution for reading out larger arrays of Microwave Kinetic Inductance Detectors (MKIDs). The ZCU111 RF SoC FPGA board from Xilinx was selected, and it is shown how this integrated system promises to increase the number of pixels that can be read out (per board) which enables a reduction in the readout cost per pixel, the mass and volume, and power consumption, all of which are important in making MKID instruments more feasible for both ground-based and space-based astrophysics. The on-chip logic capacity is shown to form a primary constraint on the number of MKIDs which can be read, channelised, and processed with this new system. As such, novel signal processing techniques are analysed, including Digitally Down Converted (DDC)-corrected sub-maximally decimated sampling, in an effort to reduce logic requirements without compromising signal to noise ratio. It is also shown how combining the ZCU111 board with a secondary FPGA board will allow all 8 ADCs and 8 DACs to be utilised, providing enough bandwidth to read up to 8,000 MKIDs per board-set, an eight-fold improvement over the state-of-the-art, and important in pursuing 100,000 pixel arrays. Finally, the feasibility of extending the operational frequency range of MKIDs to the 5 - 10 GHz regime (or possibly beyond) is investigated, and some benefits and consequences of doing so are presented.
