论文标题
近似扫描触发器以减少功能路径延迟和功耗
Approximate Scan Flip-flop to Reduce Functional Path Delay and Power Consumption
论文作者
论文摘要
基于扫描的测试已被广泛用作最新设计的设计（DFT）机制。它不仅在制造测试中，而且在在线测试和调试中都具有重要意义。但是，基于多路复用器的扫描触发器是扫描链的基本构建基础，遇到了一系列问题，例如mux引起的额外延迟和测试功率等问题。由于多路复用器对功能路径的额外延迟的影响（路径中的D）已经开始影响时钟周期，尤其是在高性能设计的较低技术节点上。在这项工作中，我们建议使用10nm Finfet技术进行两种扫描触发器设计，以解决MUX引起的延迟和内部功率的问题。拟议的设计已经过实验验证，以进行性能增益和降低功率，并与现有设计进行了比较。
The scan-based testing has been widely used as a Design-for-Test (DfT) mechanism for most recent designs. It has gained importance not only in manufacturing testing but also in online testing and debugging. However, the multiplexer-based scan flip-flop, which is the basic building block of scan chain, is troubled with a set of issues such as mux-induced additional delay and test power among others. The effect of additional delay due to the multiplexer on the functional path (D in path) has started influencing the clock period, particularly at the lower technology nodes for the high-performance design. In this work, we propose two scan flip-flop designs using 10nm FinFET technology to address the problem of mux-induced delay and internal power. The proposed designs have been experimentally validated for performance gain and power reduction and compared to the existing designs.
